1. Field of Invention
The present invention relates to a semiconductor package structure and its method of manufacture. More particularly, the present invention relates to a package structure having an array of metal pegs each linked by a printed circuit line to a silicon chip.
2. Description of Related Art
In the semiconductor industry, integrated circuits (ICs) are generally manufactured in three separate stages. First, the semiconductor substrates or silicon wafers are formed using an epitaxial technique. Next, various semiconductor devices such as MOS transistors and multi-level interconnects are formed in the semiconductor substrate. Finally, the silicon wafers are diced up to form separate dies and then packaged. The purpose of packaging is to provide the necessary protection of the die and the connection to a printed circuit board (PCB) or other electrical component.
Usually, for an IC module, a large number of connections are necessary to link up a die. Consequently, hundreds of circuit lines are needed to complete the connections. In conventional packages, a lead frame is used to connect the bonding pads on a die with external contact points outside the package. Due to the rapid increase in the level of integration of integrated circuits without a corresponding increase in size of the package, the conventional lead frame type of package is simply overwhelmed by the number of conductive wires necessary for connection. In addition, electronic products must get lighter, thinner, shorter and smaller with each upcoming generation so that they can be competitive in the marketplace. Hence, new types of packaging techniques such as chip scale package, chip size package and multi-chip module have been developed.
Nowadays, techniques for manufacturing integrated circuits having a line width smaller than 0.18 microns is available. With many breakthroughs in the level of circuit integration, the size of a package has to be minimized as well.
A conventional package uses a lead frame as a die carrier with leads protruding from the side of the package. Because these leads are distributed around the edges of the package, the package has to occupy a larger area. Furthermore, the high lead count limits the distance of separation between neighboring leads or alternatively sets up a lower boundary for the minimum area of a package. Consequently, area array package structures are invented. The contact points of an area array package are usually laid on the bottom surface of the package. For example, ball grid array (BGA), small outline no-lead (SON) and ball chip carrier (BCC) are all area array packages.
FIGS. 1A through 1E are cross-sectional views showing the progression of manufacturing steps in fabricating a conventional ball grid array type of die carrier package. First, as shown in FIG. 1A, a photoresist material is deposited over surfaces 102a and 102b of a copper substrate 100 to form photoresist layers 104a and 104b, respectively. Next, the photoresist layer 104a is exposed and developed to form ball lead areas 106 that expose a portion of the surface 102a of the copper substrate 100.
Next, as shown in FIG. 1B, a wet etching operation is conducted, etching the copper substrate 100 using the photoresist layers 104a and 104b as a mask, thereby forming hemispherical cavities 108 in the ball lead areas 106. Thereafter, an electroplating operation is carried out to form a layer of metallic film 110 over the surface of the hemispherical cavities 108.
Next, as shown in FIG. 1C, both photoresist layers 104a and 104b are removed, and then a die 112 is bonded onto the surface 102a. After that, metallic wires 114 are bonded using a wire bonding machine, thereby linking the bonding pads (not shown in the figure) on the die 112 with the metallic film 110 inside the cavities 108 (FIG. 1B).
Next, as shown in FIG. 1D, the upper surface 102a of the copper substrate 100 is sealed off using plastic material such as epoxy 116. The epoxy 116 encloses the die 112, the metallic wires 114 and the metallic film 110 inside the cavity 108 (FIG. 1B).
Next, as shown in FIG. 1E, another wet etching operation is carried out to remove the copper substrate 100 entirely (portions labeled 100 in FIG. 1D). Ultimately, the hemispherical metal films 110, the bottom portion of the die 112 and the epoxy 16 are all exposed forming a complete ball grid array type of die carrier package. This type of die carrier package utilizes the hemispherical metallic films 110 as leads for connecting with external circuits.
However, the aforementioned die carrier package has intrinsic reliability problems as well as production yield problems. Since the package uses a metallic film that is made using precious metal as a connecting lead, the metallic film must not be too thick. Yet, saving metal in plating the metallic film makes the film vulnerable to scratches or peelings during transition or transportation. Too much damage to the metallic film is liable to cause a bad connection with a printed circuit board and may ultimately lead to reliability problems when the package is finally mounted using surface mount technology (SMT). Consequently, product yield decreases.
In light of the foregoing, there is a need to provide a method for manufacturing a better type of area array package.
Accordingly, the purpose of the present invention is to provide a type of package with an array of metal pegs connected by printed circuit wires. The metal pegs can be arranged to form an area array serving as contact points of the package. This type of package structure has a smaller overall thickness. Furthermore, bottom of the die pad is exposed so that heat can be dissipated from the die more readily. Furthermore, the end face of the metal pegs is electroplated so that the metal pegs can have good bondability, molding compound characteristic and solderability.
The invention also provides a method of forming a package structure having an array of metal pegs connected by printed circuit lines. The method is capable of producing high yield and high reliability packages such that surface mount technology can be readily applied.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a package structure having an array of metal pegs connected by printed circuit lines. Structurally the package includes a die pad having a silicon die on top. The underside of the package contains a plurality of external metal pegs arranged to form an area array. Surrounding the die near the edge of the package is a number of internal metal pegs that are electrically connected to various bonding pads on the die. The die, the die pad, and the internal metal pegs are all sealed off using insulating material so that only the bottom portion of the die pad is exposed. Each external metal peg can be electrically connected to an internal metal peg via a printed circuit line. Moreover, the end face of each internal or external metal peg contains an electroplate layer.
In another aspect, this invention provides a method for forming a package having an array of metal pegs connected by printed circuit lines. The method includes the steps of providing a metal substrate, and then forming electroplated layers in the metal peg areas on both the upper and lower surface of the metal substrate. Next, photoresist layers are formed on the upper and lower surface of the metal substrate. The photoresist layers cover the non-electroplated area on the lower surface of the metal substrate as well as the desired area for forming die pad on the upper surface of the metal substrate. Thereafter, the upper surface of the metal substrate is etched to remove a portion of the substrate material to form a die pad and internal metal pegs. After removing the photoresist layers, a silicon die is attached to the die pad. Then, electrical connections are made between the die and the internal metal pegs. Subsequently, insulating material is used to seal off the die, the die pad and the internal metal pegs. Next, a circuit line mask is formed inside the printed circuit line region on the lower surface of the metal substrate. Then, an etching operation is conducted to expose a portion of the insulating material and the bottom part of the die pad as well as to form external metal pegs and printed circuit lines. Each printed circuit line is used as a medium for linking each internal metal peg to an external metal peg.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.